1. Field of the Invention
The present invention relates to a process for manufacturing a semiconductor device. More particularly, the invention relates to a process for forming a device isolation region to electrically isolate a semiconductor device formed on a semiconductor substrate.
2. Description of Related Art
A selective oxidation device isolation method and a trench device isolation method are known methods for forming a device isolation region to electrically isolate a device on a surface of a semiconductor substrate. In the selective oxidation device isolation method, a silicon substrate is selectively oxidized using a patterned silicon nitride film as a mask to form the device isolation region. In the trench device isolation method, on the other hand, trench (groove) is formed on the surface of a silicon substrate by dry-etching and the trench is filled with insulating material such as silicon oxide, to from the device isolation region.
The selective oxidation method is now generally employed in view of its simple procedure, but there is a trend toward the trench device isolation method with miniaturization of the device. In the trench device isolation method, in general, a semiconductor substrate is dry-etched vertically using a gate electrode or a dummy pattern disposed on the substrate as a mask. However, silicon interfaces perpendicular to the surface to the silicon substrate form at an end part of an active region, so that an electric field may be enhanced at the end part and the trench may not be sufficiently filled with the insulating film, which causes a void at the part.
The trench device isolation method applied to a semiconductor device having an interconnection of diffusion layers which cross the device isolation region may cause failure in connection. This is because, when impurity ions are implanted for forming the interconnection of the diffusion layers, impurity ions are insufficiently implanted into a vertical sidewall of the trench.
To solve these problems, a method for forming the device isolation region using a trench having an arc-shaped sidewall is disclosed in Japanese Unexamined Patent Publication No. HEI 7(1995)-235590.
More particularly, as shown in FIG. 3(a), a dummy pattern constituted of a silicon oxide film 24, a polycrystalline silicon film 23 and a silicon oxide film 22 are formed on a silicon semiconductor substrate 21.
Then, as shown in FIG. 3(b), a sidewall spacer 25 of silicon oxide film is formed on a sidewall of the dummy pattern using a mixture gas of SiCl.sub.4 and oxygen. Then, as shown in FIG. 3(c), the silicon semiconductor substrate 21 is etched with sputtering the sidewall spacer 25 to form trenches having an arc-shaped sidewall. Thus, the enhancement of the electric field at the sidewall of the trench can be eased. Further, the trench is wider at its upper portion and narrower at its bottom. This configuration facilitates the embedding of insulating material in the bottom portion of the trench 26. This prevents occurrence of a void. Moreover, since the sidewall of the trench 26 is arc-shaped, impurity ions for forming interconnections of diffusion layers can easily be implanted into the sidewall of the trench 26. In FIG. 3(c), the reference numeral 25a denotes the sidewall spacer after the formation of the trench.
However, in the above-described technique disclosed by Japanese Unexamined Patent Publication No. HEI 7(1995)-235590, since the silicon semiconductor substrate is etched with sputtering the sidewall spacer of silicon oxide film, the substrate must be etched at a higher ion energy (an RF bias power of 50 to 150 W) than in the case where an ordinary trench is formed on a silicon substrate by etching. A higher ion energy does cause greater damage to the silicon semiconductor substrate and may more possibly cause silicon crystallographic defects in the silicon semiconductor substrate, which will result in junction leak.
Furthermore, the number of steps is increased by an additional step for forming the sidewall.